Microchip Technology /ATSAME51J18A /ADC0 /CTRLA

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Interpret as CTRLA

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWRST)SWRST 0 (ENABLE)ENABLE 0 (BOTH)DUALSEL 0 (SLAVEEN)SLAVEEN 0 (RUNSTDBY)RUNSTDBY 0 (ONDEMAND)ONDEMAND 0 (DIV2)PRESCALER 0 (R2R)R2R

PRESCALER=DIV2, DUALSEL=BOTH

Description

Control A

Fields

SWRST

Software Reset

ENABLE

Enable

DUALSEL

Dual Mode Trigger Selection

0 (BOTH): Start event or software trigger will start a conversion on both ADCs

1 (INTERLEAVE): START event or software trigger will alternatingly start a conversion on ADC0 and ADC1

SLAVEEN

Slave Enable

RUNSTDBY

Run in Standby

ONDEMAND

On Demand Control

PRESCALER

Prescaler Configuration

0 (DIV2): Peripheral clock divided by 2

1 (DIV4): Peripheral clock divided by 4

2 (DIV8): Peripheral clock divided by 8

3 (DIV16): Peripheral clock divided by 16

4 (DIV32): Peripheral clock divided by 32

5 (DIV64): Peripheral clock divided by 64

6 (DIV128): Peripheral clock divided by 128

7 (DIV256): Peripheral clock divided by 256

R2R

Rail to Rail Operation Enable

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